1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and in particular, to a data output circuit for a semiconductor memory apparatus.
2. Related Art
In conventional semiconductor memory apparatus, a given modulation scheme, for example, PAM (Phase Amplitude Modulation), is used in order to implement high-speed operation. For example, in a 2-PAM mode, two voltage levels are used to encode data, and in a 4-PAM mode, four voltage levels are used to encode data.
As shown in FIG. 1, a conventional 4-PAM mode data output circuit includes a first output driver 10 and a second output driver 20. The first output driver 10 includes first and second resistive elements R1 and R2, and first to third transistors N1 to N3. The second output driver 20 includes fourth to sixth transistors N4 to N6.
The first to third transistors N1 to N3 of the first output driver 10 have a different size from the fourth to sixth transistors N4 to N6 of the second output driver 20. Accordingly, the amount of current supplied to a ground terminal VSS through the first transistor N1 of the first output driver 10 is different from the amount of current supplied to the ground terminal VSS through the fourth transistor N4 of the second output driver 20.
It is assumed that the amount of current supplied to the ground terminal VSS through the first transistor N1 of the first output driver 10 is “I”, and the amount of current supplied to the ground terminal VSS through the fourth transistor N4 of the second output driver 20 is “n*I”.
An output signal ‘OUT’ is output based on a first data signal ‘Data0’ and a second data signal ‘Data1’. The voltage of the output signal ‘OUT’ is as follows. In this case, a first inverted data signal ‘Data0_B’ is an inverted signal of the first data signal ‘Data0’, and a second inverted data signal ‘Data1_B’ is an inverted signal of the second data signal ‘Data1’.
If the first data signal ‘Data0’ and the second data signal ‘Data1’ are both at low level, then the voltage level of the output signal ‘OUT’ is at VDD-R2*(I+nI).
If the first data signal ‘Data0’ is at a low level and the second data signal ‘Data1’ is at a high level, then the voltage level of the output signal ‘OUT’ is at VDD-R2*I.
If the first data signal ‘Data0’ is at a high level and the second data signal ‘Data1’ is at a low level, then the voltage level of the output signal ‘OUT’ is at VDD-R2*nI.
If the first data signal ‘Data0’ and the second data signal ‘Data1’ are both at a high level, the voltage level of the output signal ‘OUT’ is at VDD.
In this way, the output signal ‘OUT’ can comprise four voltage levels and is referred to as a4 PAM (Phase Amplitude Modulation) mode.
A conventional data output circuit changes the levels of the gate voltages of the first and fourth transistors N1 and N4 to control the amount of current to be supplied to the ground terminal VSS, thereby varying the voltage level of the output signal ‘OUT’. However, when the levels of the gate voltages of the first and fourth transistor N1 and N4 are changed to control the amount of current to be supplied to the ground terminal VSS, it is difficult to linearly control the amount of current to be supplied to the ground terminal VSS. Accordingly, it is difficult to linearly vary the voltage level of the output signal ‘OUT’.